SOI Substrate


The SOI wafer is a sandwich structure with a total of three layers; including the top layer (device layer), the middle buried oxide layer (insulating SiO2 layer), and the bottom substrate (Handle silicon). SOI wafers are produced using the SIMOX method and wafer bonding technology, which can achieve thinner and more precise device layers, uniform thickness, and low defect density. SOI wafers provide good solutions for high-speed and low-power devices and are widely regarded as new solutions for high-voltage and RF devices.


Fuleda Technology can provide SOI wafers with diameters of 2″, 3″, 4″, 5″, 6″ and 8″, with a wide range of resistivity options ranging from 0.001 to 100,000 ohm-cm, from 100nm (1000Å)~ 300um wide range of device layer thickness products, suitable for a wide range of applications in the manufacture of MEMS, power devices, pressure sensors, and CMOS integrated circuits.



  



Item             


Specification           

Basic 

Spec           

Wafer Size               

50/75/100/125/150/200mm±25um                

Flat/Notch            Flat or Notch                

Device 

Layer

             
Type

  N-Type/P-Type                

Dopant                       

 B/ P/ Sb / A                

Orientation           100/110/111                
Thickness           0.1~300um                
Resistivity        

0.001~100,000ohm-cm                

Particle            <30ea@0.3                

TTV          

<10um                

Surface           Polished                
BOX                Buried Oxygen Layer Thickness        

50nm(500Å)~15um                

Handle 

Layer            

Type

N-Type/P-Type                

Dopant                B/ P/ Sb / As                
Orientation             100/110/111                
Resistivity            0.001~100,000ohm-cm                
Thickness            >100um                
Surface            Polished